1. Which bus transfers data between the CPU and main memory?
A) Address Bus
B) Control Bus
C) Data Bus
D) System Bus
✅ Answer: C) Data Bus
💡 Explanation: The Data Bus carries actual data between CPU, memory, and I/O devices bidirectionally.
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2. What is the width of the data bus in a 32-bit processor?
A) 8 bits
B) 16 bits
C) 32 bits
D) 64 bits
✅ Answer: C) 32 bits
💡 Explanation: In a 32-bit processor, the data bus is 32 bits wide, allowing 32 bits of data to be transferred at once.
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3. Which component of a CPU is responsible for arithmetic and logic operations?
A) Control Unit
B) ALU
C) Register
D) Cache
✅ Answer: B) ALU
💡 Explanation: ALU (Arithmetic Logic Unit) performs all mathematical and logical operations in the CPU.
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4. The ‘Von Neumann bottleneck’ refers to:
A) Limited CPU speed
B) Limited memory capacity
C) Limited data transfer rate between CPU and memory
D) Limited I/O speed
✅ Answer: C) Limited data transfer rate between CPU and memory
💡 Explanation: The Von Neumann bottleneck is the limited throughput (data transfer rate) between CPU and memory.
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5. Which memory is used to store the BIOS of a computer?
A) RAM
B) DRAM
C) ROM/Flash Memory
D) Cache
✅ Answer: C) ROM/Flash Memory
💡 Explanation: BIOS is stored in ROM or EEPROM/Flash memory, which is non-volatile.
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6. RISC stands for:
A) Reduced Instruction Set Computer
B) Rapid Instruction Set Computer
C) Random Instruction Set Computer
D) Reduced Internal System Computer
✅ Answer: A) Reduced Instruction Set Computer
💡 Explanation: RISC uses a small, highly optimized set of instructions to improve performance.
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7. Which type of memory is volatile?
A) ROM
B) EPROM
C) Flash Memory
D) DRAM
✅ Answer: D) DRAM
💡 Explanation: DRAM (Dynamic RAM) is volatile; it loses data when power is removed.
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8. The speed of a CPU is measured in:
A) Megabytes
B) Gigahertz
C) Megapixels
D) Teraflops
✅ Answer: B) Gigahertz
💡 Explanation: CPU speed (clock speed) is measured in GHz (Gigahertz), representing billions of cycles per second.
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9. Pipelining in a CPU is used to:
A) Increase memory
B) Increase clock speed
C) Overlap multiple instruction stages
D) Reduce power consumption
✅ Answer: C) Overlap multiple instruction stages
💡 Explanation: Pipelining allows CPU to work on multiple instruction stages simultaneously, increasing throughput.
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10. Which cache level is closest to the CPU core?
A) L3 Cache
B) L2 Cache
C) L1 Cache
D) Main Memory
✅ Answer: C) L1 Cache
💡 Explanation: L1 cache is the fastest and closest cache to the CPU core, with the smallest capacity.
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11. What does ‘overclocking’ a CPU mean?
A) Reducing power consumption
B) Running CPU at a higher speed than specified
C) Adding more cores
D) Upgrading the cooling system
✅ Answer: B) Running CPU at a higher speed than specified
💡 Explanation: Overclocking runs the CPU at a higher clock rate than its official rated speed.
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12. Which technology allows a CPU core to run two threads simultaneously?
A) Turbo Boost
B) Hyper-Threading
C) Dual-Core
D) SIMD
✅ Answer: B) Hyper-Threading
💡 Explanation: Hyper-Threading (Intel) allows one physical core to handle two threads, improving parallelism.
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13. The fetch-decode-execute cycle is also known as:
A) Boot cycle
B) Instruction cycle
C) Clock cycle
D) Memory cycle
✅ Answer: B) Instruction cycle
💡 Explanation: The fetch-decode-execute cycle is called the Instruction Cycle or Machine Cycle.
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14. Which register stores the address of the next instruction to be executed?
A) MAR
B) MBR
C) Program Counter (PC)
D) Accumulator
✅ Answer: C) Program Counter (PC)
💡 Explanation: The Program Counter (PC) always holds the memory address of the next instruction to execute.
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15. DMA stands for:
A) Direct Memory Access
B) Dynamic Memory Allocation
C) Data Management Access
D) Dual Memory Architecture
✅ Answer: A) Direct Memory Access
💡 Explanation: DMA allows hardware to access main memory independently of the CPU, speeding up I/O operations.
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16. Which type of ROM can be erased using UV light?
A) PROM
B) EEPROM
C) EPROM
D) Flash ROM
✅ Answer: C) EPROM
💡 Explanation: EPROM (Erasable Programmable ROM) is erased by exposing it to ultraviolet (UV) light.
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17. SRAM is faster than DRAM because:
A) It uses capacitors
B) It does not need refreshing
C) It is larger
D) It is cheaper
✅ Answer: B) It does not need refreshing
💡 Explanation: SRAM uses flip-flops and doesn’t require periodic refreshing unlike DRAM, making it faster.
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18. What is the function of the Memory Address Register (MAR)?
A) Stores data to be written to memory
B) Stores the address of memory to be accessed
C) Counts instructions
D) Stores arithmetic results
✅ Answer: B) Stores the address of memory to be accessed
💡 Explanation: MAR holds the memory address that the CPU wants to read from or write to.
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19. Which bus carries signals that control communication on the system bus?
A) Data Bus
B) Address Bus
C) Control Bus
D) Expansion Bus
✅ Answer: C) Control Bus
💡 Explanation: The Control Bus carries control signals like read/write commands, interrupts, and clock signals.
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20. Multi-core processors improve performance by:
A) Increasing clock speed
B) Adding more cache memory
C) Allowing parallel processing of tasks
D) Reducing instruction set
✅ Answer: C) Allowing parallel processing of tasks
💡 Explanation: Multi-core processors contain multiple CPU cores on one chip, enabling parallel execution of tasks.